The processes for fabricating MOS (metal oxide semiconductors) devices includes process steps for forming isolation regions that contain dielectric materials that provide the necessary protection for assuring proper function of the formed electronic integrated circuits, such as by minimizing leakage currents between individual devices. The various processes includes LOCOS which is an abbreviation for localized oxidation of silicon. The LOCOS process typically begins by depositing a silicon nitride layer over a silicon dioxide layer to a thickness in the range of 0.05 .mu.m. to 0.20 .mu.m. The silicon nitride layer is typically deposited using low-pressure chemical vapor deposition (LPCVD) techniques. A photoresist mask layer, comprising any appropriate commercially available photoresist material is then deposited over the silicon nitride layer and patterned by methods known in the industry. After etching the unprotected silicon nitride portions delineated by the photoresist mask and stripping the photoresist mask, a plurality of spaced apart silicon nitride regions remain on the substrate, see generally FIG. 1. The silicon nitride regions prevent oxidation of the underlying regions during a thermal oxidation process used to grow oxide isolation regions, see generally FIG. 2. The thickness of the grown oxide isolation regions is on the order of 0.10 .mu.m to 0.50 .mu.m. Subsequent to the formation of the oxide isolation regions the silicon nitride and silicon dioxide layer regions are removed by selectively wet etching to expose the active region which will be used to form the various integrated circuit components. The wet etching is typically done using hot phosphoric acid to first selectively etch the silicon nitride layer, then by dipping the substrate in a hydrofluoric acid (HF) dip to primarily etch away the silicon thin dioxide layer and prepare a clean surface upon which to form a uniform thin oxide. The process continues by growing a thin oxide layer that primarily covers the exposed active region, but also adds to the thickness of the previously grown oxide isolation regions. By example, the process further continues by deposition of a polysilicon layer over the oxide isolation regions and the thin oxide layer. FIG. 3 shows a substrate structure after having applied a photoresist mask for defining the polysilicon layer over the active region and thus forming a floating gate region.
As seen from the foregoing, formation of the oxide isolation region, in accordance with prior art techniques, involves an etching process that removes the oxide and silicon nitride in regions adjacent to those that will protect the active substrate regions during the subsequent LOCOS process. The prior art process involves a substantial number of fabrication steps that impact the cost of the product. Thus, a need is seen to exist for a method of forming the oxide isolation regions without etching and that minimizes the fabrication steps to produce semiconductor devices. Further, in order to maximize the number of devices that can fit into a given area, it is desirable to make floating gates as small as possible. For good electrical properties this means that the floating gates should be just large enough to cover the active areas beneath them. However, in practice, and since the floating gate and the active area structures are formed in two separate masking steps, the floating gate mask can be misaligned with respect to the active area. As a consequence, the floating gate has to be made larger than the ideal minimum size to account for manufacturing tolerances in aligning the two masking layers, as well as for size variations in the floating gate and active region that occur as a natural part of the masking process.
Accordingly, a primary object of the present invention is to provide a method for forming oxide isolation regions without etching and that minimizes the fabrication steps to produce semiconductor device, such as semiconductor devices having a floating gate structure.
Accordingly, another primary object of the present invention is to provide a method that defines a floating gate and active area simultaneously with one mask and thereby allowing formation of a minimum-sized floating gate structure.